Typically, processor systems are and board level designs are composed of one or more processors coupled to one or more of memory devices, glue logic, control logic, PALs, PLAs, programmable peripherals, UARTs, direct memory access controllers, memory management units, programmable A/D and D/A converters, timers, and other known peripheral devices. Most of these peripherals are coupled to a subset of the address bus, enabling processor accessibility to the peripheral's internal registers. In addition, each peripheral has a pin/terminal which is used as a chip select. The chip selects (CS) are usually one-hot and are used to select one peripheral chip out of a plurality of peripheral chips. Using the CS pins, a system designer has to map each of the peripherals to a specific address space within the global address space (either virtual or physical) addressable by the processor. The specific address spaces for peripherals are chosen so that there is no overlap between any two address spaces for the peripherals. This mapping process is done during the board level design and is implemented in hardware using either PALs, programmable control, or discrete logic.
The use of these PALs, programmable control, or discrete logic to set up an address space for peripherals has various disadvantages. An external decoder, implemented via PALs for example, is required when using this method (see prior art FIG. 1 herein). In FIG. 1, a master device 10 having an optional base address register (BAR) 12 controls the address lines on the illustrated address and data bus. The master device 10 outputs an address. The decoders 18, 24, and 30 of FIG. 1 decode the address and enable, via a chip select signal, one of the devices 14, 20, and 26. When the address is decoded by the decoder, the slave devices perform another redundant decoding due to internal decoding circuitry. One of the BARs 16, 22, or 28 is selectively written if the corresponding decoder 18, 24, or 30, respectively, determines that the address provided to the address bus was for writing a BAR. In other write cases, a register within one of either slave device 14, 20, or 26 may be written or none of the devices 14, 20, and 26 may be written, depending upon the address value.
The external decoders in FIG. 1 are used to generate the CS signals for each of the peripherals coupled to the processor. The address of each peripheral is usually determined during the design of the board and is not easy to change during software development, which is usually the next stage of final production evaluation. The external decoder increases board design size and is also an added time delay for electrical signals and peripheral use.
Furthermore, some peripherals include base address registers (BARs), each of which is used to define a particular address space for its corresponding peripheral. For example, assume that a peripheral A has six locations which are byte wide and need to be set into a memory address space. A BAR, which is written with the value of 0122H (0122 hexadecimal) allows the six registers to be accessed via the addresses 0122, 0123, 0124, 0125, 0126, and 0127, respectively. A peripheral having a BAR is usually coupled to all address lines from the processor, and implements an internal full address space decoder. The addition of an external decoder in order to distinguish between various BAR peripherals is especially inefficient, since an internal decoding is performed anyway. Furthermore, many peripherals have BARs which are located at the same address. For example, if four identical peripherals A, each having a BAR, are coupled to the processor, then when the processor writes the BAR for one peripheral A, all peripherals A are set to that BAR address and all peripherals A have the same overlapping and inoperative address space. A method to set identical peripherals or peripherals with the same BAR address to different address spaces without wasteful decoders is required.